1. Field of the Invention
The present invention generally relates to programmable logic devices, and more particularly, to a programmable logic device including a Logic Element (LE) with an N-stage Look Up Table (LUT), dedicated hardware for performing a non-LUT logic function, and an over-ride element configured to selectively force a muxing stage within the LUT to select either one or more LUT configuration bit inputs or the output of the non-LUT logic function as the output of the LUT.
2. Description of Related Art
A Programmable Logic Device (PLD) is a semiconductor integrated circuit that contains fixed logic circuitry that can be programmed to perform a host of logic functions. In the semiconductor industry, PLDs are becoming increasingly popular for a number of reasons. Due to the advances of chip manufacturing technology, application specific integrated circuits (ASICs) designs have become incredibly complex. This complexity not only adds to design costs, but also the duration of time needed to develop an application specific design. To compound this problem, product life cycles are shrinking rapidly. As a result, it is often not feasible for original equipment manufacturers (OEMs) to design and use ASICs. OEMs are therefore relying more and more on PLDs. The same advances in fabrication technology have also resulted in PLDs with improved density and speed performance. Sophisticated programming software enables complex logic functions to be rapidly developed for PLDs. Furthermore, logic designs generally can also be easily migrated from one generation of PLDs to the next, further reducing product development times. The closing of the price-performance gap with ASICs and reduced product development times makes the use of PLDs compelling for many OEMs.
Most PLDs contain a two-dimensional row and column based architecture to implement custom logic. A series of row and column interconnects, typically of varying length and speed, provide signal and clock interconnects between blocks of logic on the PLD. PLDs also include basic logic elements for implementing user defined logic functions, often referred to in the industry by such names as Logic Elements (LEs), Adaptive Logic Modules (ALMs), or Complex Logic Blocks (CLBs). The basic logic elements, regardless of what they are called, usually include one or more look up table (LUTs), registers for generating registered logic outputs, adders and other circuitry to implement various logic and arithmetic functions. For the purposes of the present invention, the term Logic Element as used herein, unless otherwise specified, shall mean a generic logic element, including but not limited to ALMs, CLBs, and LEs.
The Stratix® I device is one type of commercially available PLD, offered by Altera Corporation, assignee of the present application. The Stratix® I PLD includes an array of Logic Array Blocks (LABs) arranged in rows and columns and interconnected by horizontal and vertical lines of various lengths. Each LAB includes, among other elements, ten 4-input Logic Elements or LEs, a local interconnect, and LAB wide control signals. For more information on the Stratix® I device, see for example The Stratix Architecture, Functional Description, pages 2-1 through 2-140, from the Altera Corporation, July, 2005 (Altera Internal document Number S51002-3.2), incorporated by reference herein for all purposes. The Stratix® II device is a more recently available PLD offered by the Altera Corporation. The Stratix® II device includes LABs but differs from the Stratix® I device in that the basic logic building block is an Adaptive Logic Module (ALM) instead of Logic Elements or LEs. ALMS include 6-input fracturable LUTs. For more details on the Stratix® II device, see The Stratix® II Architecture, Functional Description, pages 2-104, The Stratix® II Device handbook, Volume 1, December 2005 (Altera Document Number SII51002-4.0), also incorporated by reference herein for all purposes.
The addition function is commonly performed on PLDs. As consequence, many programmable logic vendors have included dedicated hardware for performing full or partial addition to their Logic Elements. For example, the Logic Elements on the Stratix® I device has both a 4-input LUT and dedicated hardware to generate the Carry Out signal of an adder. The dedicate hardware, however, does not generate a Sum Out signal. Instead, the Sum Out signal is routed through the LUT of the Logic Element. For Stratix I devices, the SUM OUT of the adder thus uses the normal output path used by the LUT. As a result, 2:1 muxes are provided at the output of the Logic Element. The inputs to the muxes include (i) the register output; and (ii) either the LE output or the Sum Out signal through the LE output.
In the Stratix® II device, the adder capability of the ALM was improved. The dedicated hardware is capable of generating both the Carry out and the Sum Out signals, thus implementing a full adder. This allows the LUT to be fully used to perform logic on the inputs to the adder, which enables a more powerful arithmetic capability per ALM. The tradeoff, however, is the output muxes of the ALM have to be 3:1 since there are now three possible output signals, including the ALM output, the Register output and the Sum Out signal. Unfortunately there is a relatively high penalty in using 3:1 output muxes in the ALM because additional die area is required to implement the additional logic.
When the dedicated hardware for performing addition or some other non-LUT logic function is used within a Logic Element or ALM, the LUT is typically not used for performing logic functions. Therefore, the output path reserved for the LUT output can be used to route the output of the non-LUT function. In these cases, a programmable logic device having (i) a Logic Element with dedicated hardware for performing a non-LUT logic function (e.g., and adder) and capable of generating a non-LUT logic function output; and (ii) an over-ride element, coupled to the LUT, and configured to selectively force a muxing stage within the LUT to select either one or more configuration bit inputs, or the non-LUT logic function output, and which can be used to minimize the area cost in implementing the output path for the non-LUT logic, is therefore needed.